The present invention relates to digital-to-analog converters (DAC) and more specifically to the adjustment of such devices to compensate for errors.
Digital to analog conversion describes the process of taking a value represented in digital code and converting it to an analog signal proportional to the digital value. A variety of commercially available DACs are offered by numerous semiconductor manufacturers and electronic distributors for a wide variety of applications. DAC complexity, operating speed, and resolution is dependent upon numerous items such as internal construction, operating environment and complimentary circuitry.
The ideal DAC would be able to consistently quantitize any respective digital input to an accurate analog equivalent. In actuality deviations from the ideal operating DAC occur due in part to offset preamp voltage and voltage drop in the current path internal to the DAC. These errors are often aggravated by temperature fluctuations in the relevant operating environment.
Current DAC adjustment techniques for the above described situation focus upon calibration of the DAC at the zero and the maximum output signal levels. In applications requiring full-range accurate endpoints, current adjustment methods are deficient.
The present invention disclosed and claimed by Applicant describes a method and apparatus for improving overall accuracy of DAC performance throughout its intended operational range.